analysis.h File Reference

Analysis utilities and passes for TIR. More...

#include <tvm/ir/module.h>
#include <tvm/ir/transform.h>
#include <tvm/tir/expr.h>
#include <tvm/tir/function.h>
#include <tvm/tir/op_attr_types.h>
#include <tvm/tir/stmt.h>
#include <string>

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Classes
struct	tvm::tir::ExprDeepEqual
	Compare two expressions recursively and check if they are equal to each other without var remapping. More...

Namespaces
	tvm
	runtime implementation for LibTorch/TorchScript.
	tvm::tir
	tvm::tir::transform

Functions
template<class FLambda >
void	tvm::tir::VisitPrimFuncs (const IRModule &mod, FLambda fvisit)
	Visit the PrimFuncs in the IRModule. More...
double	tvm::tir::EstimateTIRFlops (const Stmt &stmt)
	Estimate the FLOPs of a TIR fragment. More...
double	tvm::tir::EstimateTIRFlops (const IRModule &mod)
	Estimate the FLOPs of TIRs in an IRModule. More...
Array< Var >	tvm::tir::UndefinedVars (const Stmt &stmt, const Array< Var > &defs)
	Find undefined vars in the statement. More...
Array< Var >	tvm::tir::UndefinedVars (const PrimExpr &expr)
	Find undefined vars in the expression. More...
CallEffectKind	tvm::tir::SideEffect (const PrimExpr &expr)
	Analyze the side effect. More...
bool	tvm::tir::UsesVar (const Stmt &stmt, std::function< bool(const VarNode *)> vset_contains)
	Whether the given Stmt uses any var in the given variable set. More...
bool	tvm::tir::UsesVar (const PrimExpr &expr, std::function< bool(const VarNode *)> vset_contains)
	Whether the given PrimExpr uses any var in the given variable set. More...
bool	tvm::tir::VerifySSA (const PrimFunc &func)
	Verifies whether the IR stmt or Expr is in SSA form. That is: each Var is defined and assigned once(in Let/For) More...
bool	tvm::tir::VerifyMemory (const PrimFunc &func)
	Verify if memory accesses are legal for a specific target device type. More...
bool	tvm::tir::VerifyGPUCode (const PrimFunc &func, Map< String, PrimExpr > constraints)
	Verify the correctness of a GPU code It will check the whether the amount of memory usage or the number of threads in a block exceeds the limit. More...
Array< Array< BufferRegion > >	tvm::tir::GetBlockAccessRegion (const Block &block, const Map< Var, Buffer > &buffer_var_map)
	Auto detect the block access region according to its body stmt It will detect the access region as an array in order of appearance in AST. More...
Array< Array< BufferRegion > >	tvm::tir::GetBlockReadWriteRegion (const Block &block, const Map< Var, Buffer > &buffer_var_map)
	Auto detect the block read/write region according to its body stmt. An opaque access will be counted as both a read and a write access. More...
size_t	tvm::tir::CalculateExprComplexity (const PrimExpr &expr)
	Calculate the expresion complexity based on number of symbols it contains. More...
size_t	tvm::tir::CalculateWorkspaceBytes (const PrimFunc &func, const Integer &workspace_byte_alignment)
	Calculate the workspace size in bytes needed by the TIR allocates inside the TIR PrimFunc. More...
Map< Buffer, Optional< Stmt > >	tvm::tir::DetectBufferAccessLCA (const PrimFunc &func)
	Detect the lowest common ancestor(LCA) of buffer access, including both high-level access(BufferLoad, BufferStore) and low-level access(Load, Store and opaque access). The LCA may be a For loop or a Block. More...
bool	tvm::tir::VerifyWellFormed (const PrimFunc &func, bool assert_mode=true)
	Verify if the given TIR is well-formed. The verification includes: More...
Pass	tvm::tir::transform::VerifySSA ()
	Pass variant of VerifySSA. More...
Pass	tvm::tir::transform::VerifyMemory ()
	Pass variant of VerifyMemory. More...
Pass	tvm::tir::transform::VerifyGPUCode (Map< String, PrimExpr > constraints)
	Pass variant of VerifyGPUCode. More...
Pass	tvm::tir::transform::OOBChecker ()
	Statically check TIR code for out of bounds array access. More...

Detailed Description

Analysis utilities and passes for TIR.