state.h

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 * Licensed to the Apache Software Foundation (ASF) under one
 * or more contributor license agreements.  See the NOTICE file
 * distributed with this work for additional information
 * regarding copyright ownership.  The ASF licenses this file
 * to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance
 * with the License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing,
 * software distributed under the License is distributed on an
 * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
 * KIND, either express or implied.  See the License for the
 * specific language governing permissions and limitations
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#ifndef TVM_TIR_SCHEDULE_STATE_H_
#define TVM_TIR_SCHEDULE_STATE_H_
 
#include <tvm/ffi/reflection/registry.h>
#include <tvm/ir/module.h>
#include <tvm/tir/block_scope.h>
#include <tvm/tir/function.h>
 
#include <unordered_map>
#include <utility>
 
namespace tvm {
namespace tir {
 
struct BlockInfo {
  BlockScope scope{ffi::UnsafeInit()};
  // The properties below are information about the current block realization under its parent scope
  bool affine_binding{false};
  bool region_cover{false};
  bool stage_pipeline{false};
 
  BlockInfo() = default;
 
  explicit BlockInfo(BlockScope scope, bool affine_binding = false, bool region_cover = false,
                     bool stage_pipeline = false)
      : scope(std::move(scope)),         //
        affine_binding(affine_binding),  //
        region_cover(region_cover),
        stage_pipeline(stage_pipeline) {}
};
 
enum ScheduleDebugMask : uint32_t {
  kVerifySRefTree = 1,
  kVerifyCachedFlags = 2,
};
 
class ScheduleStateNode : public Object {
 public:
  IRModule mod;
  std::unordered_map<StmtSRef, BlockInfo, ObjectPtrHash, ObjectPtrEqual> block_info;
  std::unordered_map<const StmtNode*, StmtSRef> stmt2ref;
  int debug_mask;
  bool enable_check;
 
  static void RegisterReflection() {
    namespace refl = tvm::ffi::reflection;
    refl::ObjectDef<ScheduleStateNode>()
        .def_ro("mod", &ScheduleStateNode::mod)
        .def_ro("debug_mask", &ScheduleStateNode::debug_mask)
        .def_ro("enable_check", &ScheduleStateNode::enable_check);
  }
 
  TVM_DLL void Replace(const tir::StmtSRef& src_sref, const Stmt& tgt_stmt,
                       const ffi::Map<Block, Block>& block_sref_reuse);
  TVM_DLL void DebugVerify() const;
 
  static constexpr const bool _type_mutable = true;
  TVM_FFI_DECLARE_OBJECT_INFO_FINAL("tir.ScheduleState", ScheduleStateNode, Object);
 
  /******** Property of blocks ********/
  TVM_DLL BlockInfo GetBlockInfo(const StmtSRef& block_sref) const;
  TVM_DLL void UpdateScopeBlockInfo(const Stmt& stmt);
  BlockScope GetBlockScope(const StmtSRef& scope_root) const {
    return GetBlockInfo(scope_root).scope;
  }
  bool IsAffineBlockBinding(const StmtSRef& block_sref) const {
    return GetBlockInfo(block_sref).affine_binding;
  }
  bool IsRegionCoveredConsumer(const StmtSRef& consumer_block_sref) const {
    return GetBlockInfo(consumer_block_sref).region_cover;
  }
  bool IsStagePipeline(const StmtSRef& scope_root) const {
    return GetBlockInfo(scope_root).stage_pipeline;
  }
};
 
class ScheduleState : public ObjectRef {
 public:
  TVM_DLL explicit ScheduleState(IRModule mod, int debug_mask = 0, bool enable_check = true);
 
  TVM_FFI_DEFINE_OBJECT_REF_METHODS_NULLABLE(ScheduleState, ObjectRef, ScheduleStateNode);
};
 
}  // namespace tir
}  // namespace tvm
 
#endif  // TVM_TIR_SCHEDULE_STATE_H_