tvm_tirx.tirx.op

Contents

tvm_tirx.tirx.op#

Operators used in TIR expression.

For helpers exposing ty, omitted or None result types use core Call inference; explicit types, including Type.missing(), are retained.

Classes#

Alias	Canonical API
`TensorMapType`	`tvm_tirx.tirx.TensorMapType`
`CallFFIKernelAttr`	`tvm_tirx.tirx.CallFFIKernelAttr`

Functions#

`gpu_thread_invariant`(cond, *[, ty, loc])	Mark condition as thread invariant.
`gpu_storage_sync`(storage_scope, *[, ty, loc])	Synchronize accesses in the specified storage scope.
`kernel_replace_point`(*[, ty, loc])	Mark where a transform should replace generated kernel initialization.
`gpu_warp_shuffle`(mask, value, warp_id, ...)	Exchange value between threads inside a warp.
`gpu_warp_shuffle_up`(mask, value, offset, ...)	Copy value from a lane with lower (by offset) index relative to caller.
`gpu_warp_shuffle_down`(mask, value, offset, ...)	Copy value from a lane with higher (by offset) index relative to caller.
`gpu_warp_shuffle_xor`(mask, value, lane_mask, ...)	Copy value from a lane with index computed by src_lane_idx ^ lane_mask.
`gpu_warp_activemask`(*[, ty, loc])	Return a 32-bit mask indicates currently active threads in a calling warp.
`gpu_thread_filter`(var, pred, *[, loc, ty])	Thread-set filter escape hatch.
`gpu_active_thread_selector`(var, pred[, loc, ty])	Analysis-only active-thread selector.
`masked_load`(tensor, index, *args[, ty, loc])	Load vector lanes selected by a predicate mask.
`masked_store`(tensor, value, index, *args[, ...])	Store vector lanes selected by a predicate mask.
`gpu_thread_return`(*[, ty, loc])	Return from the current GPU thread without a function value.

Alias	Canonical API
`is_tensor_var`	`tvm_tirx.tirx.is_tensor_var`
`tensor_data_ptr`	`tvm_tirx.tirx.tensor_data_ptr`
`register_intrin_lowering`	`tvm_tirx.tirx.register_intrin_lowering`
`call_packed_lowered`	`tvm_tirx.tirx.call_packed_lowered`
`call_cpacked_lowered`	`tvm_tirx.tirx.call_cpacked_lowered`
`call_packed`	`tvm_tirx.tirx.call_packed`
`call_ffi_kernel`	`tvm_tirx.tirx.call_ffi_kernel`
`call_cpacked`	`tvm_tirx.tirx.call_cpacked`
`call_intrin`	`tvm_tirx.tirx.call_intrin`
`call_pure_extern`	`tvm_tirx.tirx.call_pure_extern`
`call_extern`	`tvm_tirx.tirx.call_extern`
`call_llvm_intrin`	`tvm_tirx.tirx.call_llvm_intrin`
`call_llvm_pure_intrin`	`tvm_tirx.tirx.call_llvm_pure_intrin`
`stack_alloca`	`tvm_tirx.tirx.stack_alloca`
`stack_make_shape`	`tvm_tirx.tirx.stack_make_shape`
`stack_make_dltensor`	`tvm_tirx.tirx.stack_make_dltensor`
`assume_always`	`tvm_tirx.tirx.assume_always`
`assume_aligned`	`tvm_tirx.tirx.assume_aligned`
`undef`	`tvm_tirx.tirx.undef`
`handle_add_byte_offset`	`tvm_tirx.tirx.handle_add_byte_offset`
`abi_field_get`	`tvm_tirx.tirx.abi_field_get`
`abi_field_set`	`tvm_tirx.tirx.abi_field_set`
`address_of`	`tvm_tirx.tirx.address_of`
`gpu_thread_allreduce`	`tvm_tirx.tirx.gpu_thread_allreduce`
`cpu_parallel_barrier`	`tvm_tirx.tirx.cpu_parallel_barrier`
`ptr_byte_offset`	`tvm_tirx.tirx.ptr_byte_offset`
`throw_last_error`	`tvm_tirx.tirx.throw_last_error`
`vector_low`	`tvm_tirx.tirx.vector_low`
`vector_high`	`tvm_tirx.tirx.vector_high`
`vector_combine`	`tvm_tirx.tirx.vector_combine`
`gpu_dp4a`	`tvm_tirx.tirx.gpu_dp4a`
`reinterpret`	`tvm_tirx.tirx.reinterpret`
`isnullptr`	`tvm_tirx.tirx.isnullptr`
`logaddexp`	`tvm_tirx.tirx.logaddexp`
`alloc_workspace`	`tvm_tirx.tirx.alloc_workspace`
`free_workspace`	`tvm_tirx.tirx.free_workspace`
`get_active_lane_mask`	`tvm_tirx.tirx.get_active_lane_mask`
`get_vscale_expr`	`tvm_tirx.tirx.get_vscale_expr`
`ignore_loop_partition`	`tvm_tirx.tirx.ignore_loop_partition`
`gpu_load_matrix_sync`	`tvm_tirx.tirx.gpu_load_matrix_sync`
`gpu_mma_sync`	`tvm_tirx.tirx.gpu_mma_sync`
`gpu_fill_fragment`	`tvm_tirx.tirx.gpu_fill_fragment`
`gpu_store_matrix_sync`	`tvm_tirx.tirx.gpu_store_matrix_sync`