Analysis#

Wrapping existing analysis utils.

tvm.tirx.analysis.analysis.verify_ssa(func: PrimFunc) → bool#

Verify if the func is in SSA form.

tvm.tirx.analysis.analysis.verify_memory(func: PrimFunc) → bool#

Verify if func contains illegal host side direct memory access.

tvm.tirx.analysis.analysis.undefined_vars(node: Stmt | Expr, defs: list[Var] | None = None) → list[Var]#

Find undefined vars in a TIR statement or expression.

Parameters:

node (Union[Stmt, Expr]) – The TIR statement or expression to be checked.
defs (Optional[List[tirx.Var]]) – The vars that is defined

Returns:

result – The undefined vars.

Return type:

List[tirx.Var]

tvm.tirx.analysis.analysis.verify_well_formed(obj: PrimFunc | IRModule, assert_mode: bool = True) → bool#

Verify definitions and buffer-load types in ordinary TIRX.

Use tvm.s_tir.analysis.verify_well_formed for schedulable blocks.

Parameters:

obj (Union[tvm.tirx.PrimFunc, tvm.ir.IRModule]) – The function or module to be verified.
assert_mode (bool) – The indicator if it raises an error when the function is not well-formed.

Returns:

result – Whether it is a well-formed TIR function.

Return type:

bool

tvm.tirx.analysis.analysis.verify_tirx_well_formed(obj: PrimFunc | IRModule, assert_mode: bool = True, device_func: bool = False) → bool#

Verify if the given TIRX is well-formed.

Parameters:

obj (Union[tvm.tirx.PrimFunc, tvm.ir.IRModule]) – The function or module to be verified.
assert_mode (bool) – The indicator if it raises an error when the function is not well-formed.
device_func (bool) – The indicator if it is a device function.

Returns:

result – Whether it is a well-formed TIRX function.

Return type:

bool

Analysis