elementwise

Covers cast, fill, the unary ops (zero, reciprocal, sqrt, exp, exp2, log2, silu), the binary ops (add, sub, mul, fdiv, maximum), and fma. Every op registers two variants — reg and smem — both at priority 10; the buffer-operand storage scope (all-local vs all-shared) is the mutually-exclusive discriminator. Scalar inputs do not have a storage scope. Each op is described by an OpSpec (a parse that builds the destination + source list, optional dtype checks, and the scalar expression applied per element).

This is the current CUDA elementwise set. Other constructors in the global Tx.tile catalog, including minimum, memset, and select, do not currently have these CUDA reg / smem variants; a call needs a variant registered by its selected target backend.

Variant	Operands	Lowering
elementwise → reg	all buffer operands local	partition induced by the local-buffer layout; op applied per-thread
elementwise → smem	all buffer operands shared	synthesized [outer, threads, vec] partition; op applied per (vectorized) element

• elementwise → reg
• elementwise → smem